The disclosure relates generally to semiconductor chip design and more specifically to electromigration improvement in select C4s.
Traditionally, high temperature C4 (Controlled Collapse Chip Connection) bumps have been used to bond a chip to a substrate with the most common and widely utilized package being an organic laminate. Chips utilizing C4 bumps are known as flip chips. Conventionally, the C4 bumps (solder bumps) are made from leaded solder, as it has superior properties. For example, lead is known to mitigate thermal coefficient (TCE) mismatch between the chip and the substrate (i.e., organic laminate). Accordingly, stresses imposed during the cooling cycle are mitigated by the C4 bumps, thus preventing delaminations or other damage from occurring to the chip or the substrate. One common leaded solder includes tin and lead (SnPb) alloys. Other non-leaded conventional solders include, in a non-exhaustive list, Sn, SnAg, SnAgCu, SnBi, SnCu, and various combinations and alloys of the preceding.
As chip functionality increases at a relatively constant chip size, and high performance chips require more power and generate higher temperatures, electromigration damage in the C4s needs to be considered more carefully. To reduce electromigration concerns in a flip chip, designers sometimes replace all of the conventional C4 bumps with high electrical current carrying capacity conductive structures, such as copper pillars or copper pedestals, and attach a solder bump to the conductive structure. These may be referred to herein as enhanced C4 bumps.
With the use of enhanced C4 bumps, the stresses imposed on the flip chip, especially during the cool-down from the chip join process, are not as well mitigated as with the use of conventional C4s. The high shear stresses caused by the TCE mismatch between the chip and organic laminate, now connected by a high current capacity conductive structure, such as a copper pedestal, may result in C4 interconnection defects (i.e., small cracks or voids in the chip metallurgy under C4 bumps). These defects are known as white bumps because they appear as white features when using acoustic micro-imaging (AMI) techniques. White bumps prevent good electrical contact to a chip's input/output (I/O) contact pad (also referred to as a last metal pad or bond pad), and may lead to the failure of a device or the entire chip.